MCP Prompts

MCP prompts are conversation starters. Each prompt generates an initial message that guides the LLM through a multi-step workflow, telling it which tools to call and in what order. Think of them as runbooks --- they encode best practices so the LLM does not have to figure out the workflow from scratch.

mcltspice provides 7 prompts covering filter design, power supply analysis, debugging, optimization, Monte Carlo yield analysis, building circuits from descriptions, and troubleshooting simulation failures.

design_filter

Walks through designing a filter circuit: selecting a topology, creating the netlist, simulating with AC analysis, measuring bandwidth, and iterating on component values.

Parameter	Type	Default	Description
filter_type	`str`	`”lowpass”`	Filter response: `lowpass`, `highpass`, `bandpass`, or `notch`.
topology	`str`	`”rc”`	Circuit topology: `rc` (1st order), `rlc` (2nd order), or `sallen-key` (active).
cutoff_freq	`str`	`”1kHz”`	Target cutoff frequency with units.

Workflow steps:

Use create_netlist to build the filter circuit
Add .ac analysis directive for a frequency sweep
Add .meas directive for -3dB bandwidth
Simulate with simulate_netlist
Use measure_bandwidth to verify the cutoff frequency
Use get_waveform to inspect the full frequency response
Adjust component values and re-simulate if needed

Design tips included in the prompt:

For RC lowpass: f_c = 1 / (2 * pi * R * C)
For 2nd-order filters: Q controls peaking; Butterworth uses Q = 0.707
Use search_spice_models to find op-amp models for active topologies

analyze_power_supply

Guides through measuring the key performance metrics of a power supply: regulation, ripple, transient response, and efficiency.

Parameter	Type	Default	Description
schematic_path	`str`	`""`	Path to the power supply schematic. If empty, the prompt asks the LLM to identify or create one first.

Workflow steps:

Use read_schematic to understand the circuit topology
Use run_drc to check for design issues
Simulate with .tran analysis, including a load step if applicable
Use analyze_waveform to measure:
- Peak-to-peak output ripple
- Settling time after load transients
- FFT of the output to identify noise frequencies
If AC analysis is available, use measure_bandwidth for loop gain

Key metrics extracted: output voltage regulation (DC accuracy), ripple voltage, load transient settling time, efficiency.

debug_circuit

A systematic debugging workflow: validate the schematic, check models, run the simulation, inspect node voltages, and isolate problems by simplifying the circuit.

Parameter	Type	Default	Description
schematic_path	`str`	`""`	Path to the problematic schematic. If empty, the prompt asks the LLM to identify it first.

Workflow steps:

Validate — Run run_drc to catch missing ground, floating nodes, duplicate component names
Check setup — Use read_schematic to review component values and connections
Verify models — Use search_spice_models to confirm all referenced models exist
Run and analyze — Simulate, then use get_waveform to inspect key node voltages and compare against expected values
Isolate — Use edit_component to simplify (replace active devices with ideal sources), then diff_schematics to track which change fixed the issue

Common issues surfaced: wrong node connections, missing bias voltages, component values off by orders of magnitude, model name mismatches.

optimize_design

An iterative optimization workflow that uses optimize_circuit and Monte Carlo analysis to tune a circuit toward a target specification.

Parameter	Type	Default	Description
circuit_type	`str`	`”filter”`	Type of circuit: `filter`, `amplifier`, `regulator`, `oscillator`.
target_spec	`str`	`”1kHz bandwidth”`	Target specification to achieve.

Workflow steps:

Use list_templates to find a suitable starting point
Create the initial circuit with create_from_template
Simulate and measure current performance
Use optimize_circuit to automatically tune component values:
- Define target metrics (bandwidth, gain, settling time)
- Specify component ranges with preferred E-series values
- The optimizer iterates (typically 10-20 simulations)
Verify the optimized design with a full simulation
Run Monte Carlo with the monte_carlo tool to check yield under tolerances

Metric targets by circuit type:

Filters: bandwidth_hz
Amplifiers: gain_db and phase_margin_deg
Regulators: settling_time and peak_to_peak (ripple)

monte_carlo_analysis

Walks through a statistical yield analysis: running many simulations with randomized component tolerances, extracting metrics from each run, and computing pass/fail statistics.

Parameter	Type	Default	Description
circuit_description	`str`	`”RC filter”`	Description of the circuit to analyze.
n_runs	`str`	`”100”`	Number of Monte Carlo iterations.

Workflow steps:

Create or identify the netlist
Use the monte_carlo tool with component tolerances:
- Resistors: 1% (0.01) or 5% (0.05)
- Capacitors: 10% (0.1) or 20% (0.2)
- Inductors: 10% (0.1)
For each run, extract key metrics using get_waveform, analyze_waveform, and measure_bandwidth
Compute statistics across all runs: mean, standard deviation, min/max, and yield percentage

Tips included in the prompt:

Use list_simulation_runs to understand stepped data
Start with 10-20 runs to verify the setup, then scale up
Set a seed for reproducible results during development
Typical tolerances: metal film resistors 1%, ceramic caps 10-20%, electrolytics 20%

circuit_from_scratch

Builds a complete circuit from a text description, offering three approaches: using a template, building from individual components, or generating a graphical schematic.

Parameter	Type	Default	Description
description	`str`	`”audio amplifier”`	Plain-text description of what circuit to build.

Three approaches offered:

Template (recommended for common circuits) — list_templates then create_from_template
Component-level — create_netlist with search_spice_models and search_spice_subcircuits for model lookup
Graphical schematic — generate_schematic to produce an .asc file that can also be opened in the LTspice GUI

Verification workflow:

run_drc to catch design issues
.op analysis to verify DC bias point
.tf analysis for gain and impedance
.ac analysis for frequency response
.tran analysis for time-domain behavior
diff_schematics to compare design iterations

troubleshoot_simulation

A diagnostic checklist for simulation failures and convergence issues. Works through the problem systematically: DRC, installation check, model verification, directive inspection, node analysis, and progressive simplification.

Parameter	Type	Default	Description
error_description	`str`	`""`	What went wrong --- error message, unexpected results, etc. If empty, the prompt runs a full diagnostic.
schematic_path	`str`	`""`	Path to the problematic schematic or netlist.

Diagnostic checklist (in order):

Design Rule Check — run_drc for missing ground, floating nodes, duplicate names, missing simulation directive
Installation — check_installation to verify Wine and LTspice
Model availability — search_spice_models and search_spice_subcircuits to confirm all referenced models exist
Simulation directive — read_schematic to inspect the directive; verify analysis type, stop time, frequency range
Node connections — read_schematic to list all components and nets; check for disconnected nodes
Run and inspect — Simulate, check the log file for convergence warnings, use get_waveform to inspect node voltages
Simplify and isolate — edit_component to swap active devices for ideal ones; remove non-essential subcircuits; test each stage independently

Common failure modes addressed:

Convergence failure: reduce timestep, add initial conditions
All-zeros output: check ground connections and source polarity
Unexpected clipping: check supply voltages and headroom
Oscillation in DC circuits: add small feedback capacitors
Model not found: verify .lib / .include paths